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| Source: Atmel Aug 11, 2009 08:00 ET Atmel Announces SiliconCity(TM) Flexible Architecture for Low-Cost Custom Defined SoC DevelopmentSiliconCity Flexible Architecture offers the density of cell-based ASICs, with fast and flexible derivative design flow SAN JOSE, Calif., Aug. 11 /PRNewswire/ -- Atmel Corporation (NASDAQ: ATML) announced today a new custom architecture for 90nm SiliconCity ASIC development, providing up to 350K gates/mm2, offering customers gate densities in the range of a standard cell ASIC. SiliconCity Flexible Architecture allows designers to create their own unique base wafer architecture for multiple product variations while generously reducing customer design time, lowering the NRE and reducing risk through design reuse. The architecture relies on the breadth of Atmel's standard microcontroller solutions, to create SoCs including the reusability and proven IP that Atmel offers through its AVR and AT91SAM standard products. Metal Programmable Cell Fabric at the heart of the technology. MPCF is Atmel's patented ASIC technology that makes the CAP(TM) (customizable microcontroller) family of products, and SiliconCity Flexible Architecture, possible. In the case of CAP, Atmel defines the platform with ARM cores and bus subsystems, peripherals and memories. SiliconCity Flexible Architecture leaves the definition of the platform up to the user. By predefining the common embedded core and bus, memory and peripheral mix, the customer has the ability to implement unique IP for multiple products. The architecture gives the customer complete control, while MPCF gives it the flexibility. MPCF offers a smaller core cell with better routing. The key to the MPCF technology is a 6 transistor core cell that is less than 3.2 square microns. In the 90 nm process, a SiliconCity Flexible Architecture ASIC yields between 300,000 and 350,000 gates per square millimeter. A novel routing scheme provides two layers of metal for interconnect, increasing gate utilization up to 90%. The combination of the higher gate density and better routability of MPCF-based SoC results in die sizes that are about half those of previous 130 nm generations. Routing & Transistor Geometry Alignment. With MPCF, the cell size is matched perfectly to the integer multiple of the routing grid and transistor pitch, which results in no wasted silicon. In addition, contacts and vias are also the same size as metal trace, which eliminates any potential overlap and provides the most effective vertical use of silicon in the design. These aspects of MPCF make targeting the exact gate size required for the design much easier and more cost effective than the typical sea-of-gates architecture common with gate arrays and some early structured ASIC products. Easy Migration from Existing Processor-plus-FPGA Designs. Many existing designs based on an industry standard microcontroller and an FPGA may be directly migrated to a SiliconCity Flexible ASIC in as little as 20 weeks from final gate-level netlist with minimal re-engineering and low initial NRE mask charges. Future iterations of designs can be implemented in just 8-12 weeks with even lower single metal mask NRE charges. Availability About Atmel
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